In recent years, generally, a memory control device that executes various control by a CPU (Central Processing Unit) has incorporated therein a flash ROM as a recording medium, such as an operating system (OS) and application software. This flash ROM has the following characteristics. (1) Even when its power is switched off, data is maintained. (2) Before data is written, erasing of a write area needs to be performed. (3) Data needs to be erased by a unit of block defined for each device, and the erasing of data is performed by applying signals to data pins of each device by a predetermined procedure. (4) Data writing is performed by applying signals to data pins of a device by a predetermined procedure.
Because the flash ROM is configured to record therein a data value by confining charges, a phenomenon referred to as “charge leakage” occasionally occurs because of a variation between data retention times of memory cells, influence of noise, and the like. A bit error occurs in data stored in the flash ROM with a certain probability by the charge leakage.
To solve such problems, in a conventional technique represented by Patent Literature 1 mentioned below, there is disclosed a recording device including the flash ROM described above as a recording medium and an error correction technique for correcting data to normal data when an error in a data value occurs in the flash ROM.